C8051T612-GQ Silicon Laboratories Inc, C8051T612-GQ Datasheet - Page 157
C8051T612-GQ
Manufacturer Part Number
C8051T612-GQ
Description
IC 8051 MCU 8K BYTE-PROG 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Specifications of C8051T612-GQ
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051FT610DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1439
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T612-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051T612-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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24. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
Figure 24.1. SPI Block Diagram
7
6
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
SPI0CFG
Control
SPI0DAT
1
SPI0DAT
Read
0
Rev 1.0
Tx Data
Rx Data
C8051T610/1/2/3/4/5/6/7
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
C
R
O
S
S
B
A
R
SPI IRQ
Port I/O
157
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