MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 227
![MCU 8BIT 16K FLASH 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08JM16CGT
Manufacturer Part Number
MC9S08JM16CGT
Description
MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM16CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC9S08JM16CGT
Manufacturer:
PIXART
Quantity:
1 001
Part Number:
MC9S08JM16CGT
Manufacturer:
FREESCALE
Quantity:
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14.2.4
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.
Freescale Semiconductor
Reset
Field
RWU
SBK
TE
RE
3
2
1
0
W
R
TDRE
SCI Status Register 1 (SCIxS1)
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output
for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
Refer to
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If
LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. Refer to
Queued
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
1
7
Section 14.3.2.1, “Send Break and Queued
Idle” for more details.
= Unimplemented or Reserved
TC
1
6
Table 14-4. SCIxC2 Field Descriptions (continued)
Figure 14-8. SCI Status Register 1 (SCIxS1)
MC9S08JM16 Series Data Sheet, Rev. 2
RDRF
0
5
IDLE
Section 14.3.3.2, “Receiver Wakeup
0
4
Description
Idle” for more details.
OR
3
0
Serial Communications Interface (S08SCIV4)
NF
0
2
Section 14.3.2.1, “Send Break and
Operation” for more details.
FE
0
1
PF
0
0
227
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