MC9S08GT8ACFBE Freescale Semiconductor, MC9S08GT8ACFBE Datasheet - Page 162

• Manufacturer Part Number: MC9S08GT8ACFBE
• Description: IC MCU 8K FLASH 1K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer/Pulse-Width Modulator (S08TPMV2)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
10.3.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written.
162
CPWMS
Reset
Reset
X
0
1
W
W
R
R
Bit 15
Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
Bit 7
0
0
7
7
MSnB:MSnA
XX
XX
1X
00
01
Figure 10-9. Timer x Channel Value Register High (TPMxCnVH)
Figure 10-10. Timer Channel Value Register Low (TPMxCnVL)
14
0
6
0
6
6
ELSnB:ELSnA
Table 10-5. Mode, Edge, and Level Selection
MC9S08GT16A/GT8A Data Sheet, Rev. 1
X1
X1
00
01
10
11
00
01
10
11
10
10
13
0
5
0
5
5
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Center-aligned
Input capture
Edge-aligned
compare
Output
12
Mode
PWM
PWM
0
4
0
4
4
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
11
3
0
3
3
0
10
0
2
0
2
2
Configuration
Freescale Semiconductor
9
0
1
0
1
1
Bit 8
Bit 0
0
0
0
0