MC9S08DN32AVLF Freescale Semiconductor, MC9S08DN32AVLF Datasheet - Page 208
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MC9S08DN32AVLF
Manufacturer Part Number
MC9S08DN32AVLF
Description
MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DN32AVLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Processor Series
S08DN
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DN32AVLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.4.3
General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches
the general call address as well as its own slave address. When the IIC responds to a general call, it acts as
a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after
the first byte transfer to determine whether the address matches is its own slave address or a general call.
If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied
from a general call address by not issuing an acknowledgement.
11.5
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
11.6
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You
can determine the interrupt type by reading the status register.
11.6.1
The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion
of byte transfer.
11.6.2
When the calling address matches the programmed slave address (IIC address register) or when the
GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is
interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
11.6.3
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
208
Resets
Interrupts
General Call Address
Byte Transfer Interrupt
Address Detect Interrupt
Arbitration Lost Interrupt
Match of received calling address
Complete 1-byte transfer
Interrupt Source
Arbitration Lost
MC9S08DN60 Series Data Sheet, Rev 3
Table 11-11. Interrupt Summary
Status
ARBL
IAAS
TCF
Table 11-11
IICIF
IICIF
IICIF
Flag
Local Enable
occur, provided the IICIE bit
IICIE
IICIE
IICIE
Freescale Semiconductor
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