MC9S08DN32AVLF Freescale Semiconductor, MC9S08DN32AVLF Datasheet - Page 57

• Manufacturer Part Number: MC9S08DN32AVLF
• Description: MCU 8BIT 32K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DN32AVLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Processor Series: S08DN
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-7
4.5.11.2
During reset, the contents of the nonvolatile location NVOPT are copied from Flash into FOPT. To change
the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue
a new MCU reset.
Freescale Semiconductor
PRDIV8
DIVLD
Field
DIV
5:0
7
6
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for Flash and EEPROM.
1 FCDIV has been written since reset; erase and program operations enabled for Flash and EEPROM.
Prescale (Divide) Flash and EEPROM Clock by 8 (This bit is write once.)
0 Clock input to the Flash and EEPROM clock divider is the bus rate clock.
1 Clock input to the Flash and EEPROM clock divider is the bus rate clock divided by 8.
Divisor for Flash and EEPROM Clock Divider — These bits are write once. The Flash and EEPROM clock
divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV
field plus one. The resulting frequency of the internal Flash and EEPROM clock must fall within the range of
200 kHz to 150 kHz for proper Flash and EEPROM operations. Program/Erase timing pulses are one cycle of
this internal Flash and EEPROM clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1
Flash and EEPROM Options Register (FOPT and NVOPT)
200 kHz
150 kHz
20 MHz
10 MHz
8 MHz
4 MHz
2 MHz
1 MHz
f
Bus
and
(Binary)
PRDIV8
Table 4-7. Flash and EEPROM Clock Divider Settings
if PRDIV8 = 1 — f
Equation
1
0
0
0
0
0
0
0
if PRDIV8 = 0 — f
Table 4-6. FCDIV Register Field Descriptions
MC9S08DN60 Series Data Sheet, Rev 3
4-2.
(Decimal)
DIV
12
49
39
19
9
4
0
0
FCLK
FCLK
= f
192.3 kHz
= f
Bus
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
f
FCLK
Description
Bus
÷ (8 × (DIV + 1))
÷ (DIV + 1)
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
5.2 μs
6.7 μs
5 μs
5 μs
5 μs
5 μs
5 μs
5 μs
Chapter 4 Memory
Eqn. 4-1
Eqn. 4-2
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