MC9S08SL16CTL Freescale Semiconductor, MC9S08SL16CTL Datasheet - Page 312
![MCU 16KB FLASH SLIC 28TSSOP](/photos/12/35/123504/mc9s08sl16ctl_sml.jpg)
MC9S08SL16CTL
Manufacturer Part Number
MC9S08SL16CTL
Description
MCU 16KB FLASH SLIC 28TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08EL32.pdf
(356 pages)
Specifications of MC9S08SL16CTL
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
S08SL
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
6
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08EL32, DEMO9S08EL32AUTO
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
28TSSOP
Family Name
HCS08
Maximum Speed
40 MHz
For Use With
DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08SL16CTL
Manufacturer:
Freescale
Quantity:
2 359
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Development Support
Figure 17-4
shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
HIGH-IMPEDANCE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES
HOST SAMPLES BKGD PIN
Figure 17-4. BDC Target-to-Host Serial Bit Timing (Logic 1)
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
314
Freescale Semiconductor
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