MC9S12P96MFT Freescale Semiconductor, MC9S12P96MFT Datasheet - Page 496

• Manufacturer Part Number: MC9S12P96MFT
• Description: MCU 16BIT 96K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P96MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer Module (TIM16B8CV2) Block Description
14.4.1
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
496
PACLK/65536
PACLK/256
Bus Clock
PAOVF
INTERRUPT
Prescaler
REQUEST
PR[2:1:0]
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG0A
EDG1A
PAOVF
TCNT(hi):TCNT(lo)
PRESCALER
16-BIT COUNTER
PAOVI
CHANNEL2
CHANNEL 1
CHANNEL7
CHANNEL 0
PACNT(hi):PACNT(lo)
TC0
TC1
TC7
16-BIT COUNTER
EDG7A
EDG7B
EDG0B
EDG1B
INTERRUPT
PAOVI
LOGIC
PACLK/65536
PAOVF
PACLK/256
Figure 14-30. Detailed Timer Block Diagram
PACLK
S12P-Family Reference Manual, Rev. 1.13
CLEAR COUNTER
DETECT
DETECT
TE
DETECT
EDGE
EDGE
EDGE
PAIF
C0F
C1F
C7F
PAI
PACLK
MUX
OM:OL1
OM:OL0
TOV1
OM:OL7
TOV0
TOV7
CLK[1:0]
DIVIDE-BY-64
TOF
TOI
PAMOD
PEDGE
IOC0
CxF
CxI
C0F
C1F
PAE
IOC1
C7F
IOC7
INTERRUPT
LOGIC
IOC0 PIN
IOC1 PIN
IOC7 PIN
LOGIC
LOGIC
LOGIC
DETECT
EDGE
PAIF
channel 7 output
compare
TCRE
CH. 1 COMPARE
CH. 0 CAPTURE
CH. 1 CAPTURE
CH. 0COMPARE
CH. 7 COMPARE
CH.7 CAPTURE
PA INPUT
Freescale Semiconductor
Bus Clock
IOC0 PIN
IOC1 PIN
IOC7 PIN
TOF