MC9S12P96MFT Freescale Semiconductor, MC9S12P96MFT Datasheet - Page 96

• Manufacturer Part Number: MC9S12P96MFT
• Description: MCU 16BIT 96K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P96MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime. The data source is depending on the data direction value.
Port Integration Module (S12PPIMV1)
2.3.56
2.3.57
96
Function
Address 0x026F
Address 0x0270
7-6, 2-0
Write: Anytime
Write: Anytime
PT0AD
Altern.
Field
Field
PIFJ
Reset
Reset
1-0
W
W
R
R
Port J interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Port AD general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
PIFJ7
Port J Interrupt Flag Register (PIFJ)
Port AD Data Register (PT0AD)
—
0
0
0
7
7
PIFJ6
—
0
0
0
6
6
Figure 2-54. Port J Interrupt Flag Register (PIFJ)
Table 2-51. PT0AD Register Field Descriptions
Table 2-50. PIFJ Register Field Descriptions
Figure 2-55. Port AD Data Register (PT0AD)
S12P-Family Reference Manual, Rev. 1.13
—
5
0
0
5
0
0
—
0
0
0
0
4
4
Description
Description
—
0
0
0
0
3
3
PIFJ2
—
0
0
0
2
2
Access: User read/write
Access: User read/write
PT0AD1
Freescale Semiconductor
PIFJ1
AN9
0
0
1
1
PT0AD0
PIFJ0
AN8
0
0
0
0
(1)
(1)