MCF52210CAE66 Freescale Semiconductor, MCF52210CAE66 Datasheet - Page 23

• Manufacturer Part Number: MCF52210CAE66
• Description: IC MCU 64K FLASH 66MHZ 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5221xr

Specifications of MCF52210CAE66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: MCF522x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/QSPI/UART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 43
• Number Of Timers: 18
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Package: 64LQFP
• Device Core: ColdFire
• Family Name: MCF5221x
• Maximum Speed: 66 MHz
• For Use With: M52210DEMO - BOARD DEV MCF5221X LOW COST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.10
Table 11
1.11
Table 12
Freescale Semiconductor
Transmit Serial Data
Receive Serial Data
DMA Timer Output
Request-to-Send
DMA Timer Input
describes the UART module signals.
describes the signals of the four DMA timer modules.
Clear-to-Send
Signal Name
Signal Name
Signal Name
Serial Clock
Serial Data
UART Module Signals
DMA Timer Signals
Output
Input
Abbreviation
Abbreviation
Abbreviation
DTOUT
URXDn
UTXDn
UCTSn
URTSn
SDAn
SCLn
DTIN
MCF52211 ColdFire Microcontroller, Rev. 2
Table 11. UART Module Signals
Open-drain clock signal for the for the I
In master mode, this clock is driven by the I
is in slave mode, this clock becomes the clock input.
Open-drain signal that serves as the data input/output for the I
interface.
Event input to the DMA timer modules.
Programmable output from the DMA timer modules.
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, LSB first, on this pin at
the falling edge of the serial clock source.
Receiver serial data inputs for the UART modules. Data is received on
this pin LSB first. When the UART clock is stopped for power-down
mode, any transition on this pin restarts the clock.
Indication to the UART modules that they can begin data
transmission.
Automatic request-to-send outputs from the UART modules. This
signal can also be configured to be asserted and negated as a
function of the RxFIFO level.
Table 12. DMA Timer Signals
Table 10. I
2
C I/O Signals
Function
Function
Function
2
C interface. When the bus is
2
C module; when the bus
Family Configurations
2
C
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
23