C8051F311-GMR Silicon Laboratories Inc, C8051F311-GMR Datasheet - Page 159

• Manufacturer Part Number: C8051F311-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F311-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• For Use With: 336-1446 - ADAPTER PROGRAM TOOLSTICK F311336-1253 - DEV KIT FOR C8051F310/F311
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 14.7 shows a typical Slave
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received.
Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 14.7. Typical Slave Receiver Sequence
SLA
Interrupt
W
A
Data Byte
Rev. 1.7
Interrupt
C8051F310/1/2/3/4/5/6/7
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
Interrupt
A
Interrupt
P
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