MC9S08DZ96CLF Freescale Semiconductor, MC9S08DZ96CLF Datasheet - Page 410
![MCU 8BIT 96K FLASH 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ96CLF
Manufacturer Part Number
MC9S08DZ96CLF
Description
MCU 8BIT 96K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ96CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
6 KB
Interface Type
CAN/I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
87
Number Of Timers
3
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ96CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 18 Debug Module (S08DBGV3) (128K)
18.4
This section provides a complete functional description of the on-chip ICE system. The DBG module is
enabled by setting the DBGEN bit in the DBGC register. Enabling the module allows the arming,
triggering and storing of data in the FIFO. The DBG module is made up of three main blocks, the
Comparators, Trigger Break Control logic and the FIFO.
18.4.1
The DBG module contains three comparators, A, B, and C. Comparator A compares the core address bus
with the address stored in the DBGCAX, DBGCAH, and DBGCAL registers. Comparator B compares the
core address bus with the address stored in the DBGCBX, DBGCBH, and DBGCBL registers except in
full mode, where it compares the data buses to the data stored in the DBGCBL register. Comparator C
compares the core address bus with the address stored in the DBGCCX, DBGCCH, and DBGCCL
registers. Matches on Comparators A, B, and C are signaled to the Trigger Break Control (TBC) block.
18.4.1.1
In full modes ("A And B" and "A And Not B") RWAEN and RWA are used to select read or write
comparisons for both comparators A and B. To select write comparisons and the write data bus in Full
Modes set RWAEN=1 and RWA=0, otherwise read comparisons and the read data bus will be selected.
The RWBEN and RWB bits are not used and will be ignored in Full Modes.
18.4.1.2
Normally comparator C is used as a third hardware breakpoint and is not involved in the trigger logic for
the on-chip ICE system. In this mode, it compares the core address bus with the address stored in the
DBGCCX, DBGCCH, and DBGCCL registers. However, in LOOP1 capture mode, comparator C is
managed by logic in the DBG module to track the address of the most recent change-of-flow event that
was captured into the FIFO buffer. In LOOP1 capture mode, comparator C is not available for use as a
normal hardware breakpoint.
When the ARM and DBGEN bits are set to one in LOOP1 capture mode, comparator C value registers are
cleared to prevent the previous contents of these registers from interfering with the LOOP1 capture mode
operation. When a COF event is detected, the address of the event is compared to the contents of the
DBGCCX, DBGCCH, and DBGCCL registers to determine whether it is the same as the previous COF
entry in the capture FIFO. If the values match, the capture is inhibited to prevent the FIFO from filling up
with duplicate entries. If the values do not match, the COF event is captured into the FIFO and the
DBGCCX, DBGCCH, and DBGCCL registers are updated to reflect the address of the captured COF
event. When comparator C is updated, the PAGSEL bit (bit-7 of DBGCCX) is updated with the PPACC
value that is captured into the FIFO. This bit indicates whether the COF address was a paged 17-bit
program address using the PPAGE mechanism (PPACC=1) or a 17-bit CPU address that resulted from an
unpaged CPU access.
410
Functional Description
Comparator
RWA and RWAEN in Full Modes
Comparator C in LOOP1 Capture Mode
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
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