MC9S08RD32DWE Freescale Semiconductor, MC9S08RD32DWE Datasheet - Page 79

• Manufacturer Part Number: MC9S08RD32DWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32DWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.6.2
Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction
(PTBDD), and pullup enable (PTBPE) registers.
Freescale Semiconductor
PTADD[7:0]
PTBD[7:0]
Field
Field
7:0
7:0
Reset
Reset
W
W
R
R
Port B Registers (PTBD, PTBPE, and PTBDD)
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
PTADD7
PTBD7
0
0
7
7
PTADD6
PTBD6
6
0
6
0
Figure 6-8. Data Direction for Port A (PTADD)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Figure 6-9. Port B Data Register (PTBD)
Table 6-3. PTADD Field Descriptions
Table 6-4. PTBD Field Descriptions
PTADD5
PTBD5
0
0
5
5
PTADD4
PTBD4
4
0
4
0
Description
Description
PTADD3
PTBD3
0
0
3
3
PTADD2
PTBD2
2
0
2
0
PTADD1
PTBD1
0
0
1
1
Parallel Input/Output
PTADD0
PTBD0
0
0
0
0
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