C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 227

IC 8051 MCU 8K FLASH 28MLP

C8051F351-GMR

Manufacturer Part Number
C8051F351-GMR
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Datasheets

Specifications of C8051F351-GMR

Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x24b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
24 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
For Use With
336-1083 - DEV KIT FOR F350/351/352/353
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
24. Revision Specific Behavior
This chapter describes a functional difference between C8051F35x “REV B” and “REV C” or later devices.
The functionality of the VREF- pin differs between these revisions.
24.1. Revision Identification
The Lot ID Code on the top side of the device package can be used for decoding device revision informa-
tion. On C8051F350/2 devices, the revision letter is the first letter of the Lot ID Code. On C8051F351/3
devices, the revision letter is the first of the Lot ID Code. Figure 24.1 shows how to find the revision on the
top side of the device package.
24.1. VREF- pin
The required connection for the VREF- pin differs between the "REV B" and "REV C" and later devices.
On "REV B" devices, when the internal voltage reference is enabled, the VREF- pin is internally connected
to GND so the VREF- pin can be left unconnected externally.
On "REV C" and later devices, when the internal voltage reference is enabled, the VREF- pin is not inter-
nally connected to GND. The VREF- pin must be connected to GND externally for the voltage reference to
operate properly.
Revision Letter
C8051F350/2 Package Marking
C8051F350
CCNAVT
0450
Figure 24.1. Reading Package Marking
Rev. 1.1
Revision Letter
C8051F351/3 Package Marking
SILABS
F351
CCNAKX
0537+
C8051F350/1/2/3
227

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