C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 87
![IC 8051 MCU 8K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F351-GMR
Manufacturer Part Number
C8051F351-GMR
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F351-GMR
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x24b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
24 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
For Use With
336-1083 - DEV KIT FOR F350/351/352/353
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (2Mb)
10. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The C8051F35x family has a superset of all the peripherals included with a standard 8051. See Sec-
tion “1. System Overview’ on page 17 for more information about the available peripherals. The CIP-51
includes on-chip debug hardware which interfaces directly with the analog and digital subsystems, provid-
ing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51 core includes the following features:
- Fully Compatible with MCS-51 Instruction
- 50 MIPS Peak Throughput
- 256 Bytes of Internal RAM
Set
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
Figure 10.1. CIP-51 Block Diagram
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
Rev. 1.1
TMP2
DATA BUS
DATA BUS
D8
D8
D8
A16
D8
D8
D8
D8
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- Integrated Debug Logic
B REGISTER
REGISTER
INTERRUPT
ADDRESS
INTERFACE
INTERFACE
INTERFACE
MEMORY
SRAM
SFR
BUS
C8051F350/1/2/3
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
87
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