MC908AP32CFBER Freescale Semiconductor, MC908AP32CFBER Datasheet - Page 297
![IC MCU 32K FLASH 8MHZ 44-QFP](/photos/19/2/190263/4533613_sml.jpg)
MC908AP32CFBER
Manufacturer Part Number
MC908AP32CFBER
Description
IC MCU 32K FLASH 8MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908AP32CFBER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP32CFBER
Manufacturer:
FREESCALE
Quantity:
5 000
Company:
Part Number:
MC908AP32CFBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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21.5.4 SIM Break Flag Control Register
The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while
the MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
Freescale Semiconductor
;
;
;
;
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the break
service routine software.
HIBYTE
LOBYTE
DOLO
RETURN
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
EQU
EQU
If not SBSW, do RTI
BRCLR
TST
BNE
DEC
DEC
PULH
RTI
Address:
Reset:
Read:
Write:
5
6
SBSW,SBSR, RETURN
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
$FE03
Figure 21-7. SIM Break Flag Control Register (SBFCR)
BCFE
Bit 7
R
0
= Reserved
R
6
MC68HC908AP Family Data Sheet, Rev. 4
R
5
;
;
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
See if wait mode or stop mode was exited by
break.
R
4
R
3
R
2
R
1
Break Module Registers
Bit 0
R
295
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