MC908AP32CFBER Freescale Semiconductor, MC908AP32CFBER Datasheet - Page 98
![IC MCU 32K FLASH 8MHZ 44-QFP](/photos/19/2/190263/4533613_sml.jpg)
MC908AP32CFBER
Manufacturer Part Number
MC908AP32CFBER
Description
IC MCU 32K FLASH 8MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908AP32CFBER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP32CFBER
Manufacturer:
FREESCALE
Quantity:
5 000
Company:
Part Number:
MC908AP32CFBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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System Integration Module (SIM)
98
$FE00
$FE01
$FE03
Addr.
PIN LOGIC
RESET
Note: Writing a logic 0 clears SBSW.
SIM Break Status Register
SIM Reset Status Register
SIM Break Flag Control
Register Name
Register (SBFCR)
V
DD
INTERNAL
PULLUP
DEVICE
(SRSR)
(SBSR)
SIM RESET STATUS REGISTER
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
POR:
RESET PIN CONTROL
Figure 7-2. SIM I/O Register Summary
POR CONTROL
AND PRIORITY DECODE
STOP/WAIT
INTERRUPT CONTROL
CONTROL
CONTROL
MC68HC908AP Family Data Sheet, Rev. 4
CLOCK
BCFE
Bit 7
POR
Figure 7-1. SIM Block Diagram
R
0
1
0
PIN
R
R
CLOCK GENERATORS
6
0
0
RESET
COUNTER
SIM
COP
÷ 2
R
R
5
0
0
CONTROL
MASTER
RESET
ILOP
R
R
4
0
0
ILAD
R
R
3
0
0
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
MODRST
R
R
2
0
0
Freescale Semiconductor
SBSW
NOTE
LVI
R
1
0
0
Bit 0
R
R
0
0
0
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