MC908GZ32VFAER Freescale Semiconductor, MC908GZ32VFAER Datasheet - Page 96
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MC908GZ32VFAER
Manufacturer Part Number
MC908GZ32VFAER
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GZ60CFJE.pdf
(352 pages)
Specifications of MC908GZ32VFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GZ32VFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Computer Operating Properly (COP) Module
The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration
register. With a 262,128 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout
period of 53.3 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset
by clearing the COP counter and stages 12–5 of the SIM counter.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at V
V
6.3 I/O Signals
The following paragraphs describe the signals shown in
6.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) clears the COP counter and clears stages 12–5
of the SIM counter. Reading the COP control register returns the low byte of the reset vector. See
COP Control Register.
6.3.4 Power-On Reset
The power-on reset (POR) circuit clears the SIM counter 4096 CGMXCLK cycles after power-up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
96
TST
on the RST pin disables the COP.
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
NOTE
NOTE
Figure
6-1.
TST
. During the break state,
Freescale Semiconductor
6.4
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