C8051F504-IQ Silicon Laboratories Inc, C8051F504-IQ Datasheet - Page 130
![IC 8051 MCU 32K FLASH 48-QFP](/photos/12/36/123620/c8051f504-iq_sml.jpg)
C8051F504-IQ
Manufacturer Part Number
C8051F504-IQ
Description
IC 8051 MCU 32K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F504-IQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1518
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F504-IQ
Manufacturer:
Silicon Labs
Quantity:
135
Company:
Part Number:
C8051F504-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
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Company:
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C8051F504-IQR
Manufacturer:
Silicon Laboratories Inc
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C8051F50x/F51x
15.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
1. Disable interrupts (recommended).
2. Erase the 512-byte Flash page containing the target location, as described in Section 15.1.2.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
Steps 5–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory.
15.1.4. Flash Write Optimization
The Flash write procedure includes a block write option to optimize the time to perform consecutive byte
writes. When block write is enabled by setting the CHBLKW bit (CCH0CN.0), writes to two consecutive
bytes in Flash require the same amount of time as a single byte write. This is performed by caching the first
byte that is written to Flash and then committing both bytes to Flash when the second byte is written. When
block writes are enabled, if the second write does not occur, the first data byte written is not actually written
to Flash. Flash bytes with block write enabled are programmed by software with the following sequence:
1. Disable interrupts (recommended).
2. Erase the 512-byte Flash page containing the target location, as described in Section 15.1.2.
3. Set the CHBLKW bit (register CCH0CN).
4. Set the PSWE bit (register PSCTL).
5. Clear the PSEE bit (register PSCTL).
6. Write the first key code to FLKEY: 0xA5.
7. Write the second key code to FLKEY: 0xF1.
8. Using the MOVX instruction, write the first data byte to the desired location within the 512-byte sector.
9. Write the first key code to FLKEY: 0xA5.
10.Write the second key code to FLKEY: 0xF1.
11. Using the MOVX instruction, write the second data byte to the desired location within the 512-byte
sector. The location of the second byte must be the next higher address from the first data byte.
12.Clear the PSWE bit.
13.Clear the CHBLKW bit.
130
Rev. 1.2
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