C8051F504-IQ Silicon Laboratories Inc, C8051F504-IQ Datasheet - Page 8

• Manufacturer Part Number: C8051F504-IQ
• Description: IC 8051 MCU 32K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1518

C8051F50x/F51x
List of Figures
8
Figure 1.1. C8051F500/1/4/5 Block Diagram .......................................................... 17
Figure 1.2. C8051F508/9-F510/1 Block Diagram .................................................... 18
Figure 1.3. C8051F502/3/6/7 Block Diagram .......................................................... 19
Figure 3.1. QFP-48 Pinout Diagram (Top View) ...................................................... 25
Figure 3.2. QFN-48 Pinout Diagram (Top View) ..................................................... 26
Figure 3.3. QFN-40 Pinout Diagram (Top View) ..................................................... 27
Figure 3.4. QFP-32 Pinout Diagram (Top View) ...................................................... 28
Figure 3.5. QFN-32 Pinout Diagram (Top View) ..................................................... 29
Figure 4.1. QFP-48 Package Drawing ..................................................................... 30
Figure 4.2. QFP-48 Landing Diagram ..................................................................... 31
Figure 4.3. QFN-48 Package Drawing .................................................................... 32
Figure 4.4. QFN-48 Landing Diagram ..................................................................... 33
Figure 4.5. Typical QFN-40 Package Drawing ........................................................ 34
Figure 4.6. QFN-40 Landing Diagram ..................................................................... 35
Figure 4.7. QFP-32 Package Drawing ..................................................................... 36
Figure 4.8. QFP-32 Package Drawing ..................................................................... 37
Figure 4.9. QFN-32 Package Drawing .................................................................... 38
Figure 4.10. QFN-32 Package Drawing .................................................................. 39
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency ........... 44
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 52
Figure 6.2. ADC0 Tracking Modes .......................................................................... 54
Figure 6.3. 12-Bit ADC Tracking Mode Example ..................................................... 55
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 56
Figure 6.5. ADC0 Equivalent Input Circuit ............................................................... 58
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 69
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 69
Figure 6.8. ADC0 Multiplexer Block Diagram .......................................................... 70
Figure 7.1. Temperature Sensor Transfer Function ................................................ 72
Figure 8.1. Voltage Reference Functional Block Diagram ....................................... 73
Figure 9.1. Comparator Functional Block Diagram ................................................. 75
Figure 9.2. Comparator Hysteresis Plot .................................................................. 76
Figure 9.3. Comparator Input Multiplexer Block Diagram ........................................ 81
Figure 10.1. External Capacitors for Voltage Regulator Input/Output—
Figure 10.2. External Capacitors for Voltage Regulator Input/Output—
Figure 11.1. CIP-51 Block Diagram ......................................................................... 87
Figure 12.1. C8051F50x-F51x Memory Map ........................................................... 97
Figure 12.2. Flash Program Memory Map ............................................................... 98
Figure 13.1. SFR Page Stack ................................................................................ 101
Figure 13.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT . 102
Figure 13.3. SFR Page Stack After CAN0 Interrupt Occurs .................................. 103
Figure 13.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR 104
Regulator Enabled .............................................................................. 84
Regulator Disabled ............................................................................. 85
Rev. 1.2