R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet - Page 143

• Manufacturer Part Number: R5F21292SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21292SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
12.5
Figure 12.19
Table 12.9
Timer RC
Clock synchronous serial
I/O with chip select
I
2
The timer RC interrupt, clock synchronous serial I/O with chip select interrupt, and I
have multiple interrupt request sources. An interrupt request is generated by the logical OR of several interrupt
request factors and is reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these
peripheral functions has its own interrupt request source status register (status register) and interrupt request source
enable register (enable register) to control the generation of interrupt requests (change the IR bit in the interrupt
control register). Table 12.9 lists the Registers Associated with Timer RC Interrupt, Clock Synchronous Serial I/O
with Chip Select Interrupt, and I
Interrupt.
C bus interface
Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupts, and I
Request Sources)
Sep 26, 2008
Chip Select Interrupt, and I
Registers Associated with Timer RC Interrupt, Clock Synchronous Serial I/O with
Block Diagram of Timer RC Interrupt
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
Page 124 of 441
TRCSR
SSSR
ICSR
Interrupt Request Source
2
IMIEC bit
IMIED bit
IMIEA bit
IMIEB bit
C bus Interface Interrupt (Interrupts with Multiple Interrupt
IMFC bit
IMFD bit
IMFA bit
IMFB bit
OVIE bit
OVF bit
2
Status Register of
C bus Interface Interrupt and Figure 12.19 shows a Block Diagram of Timer RC
2
C bus Interface Interrupt
Interrupt Request Source
TRCIER
SSER
ICIER
Enable Register of
Timer RC
interrupt request
(IR bit in TRCIC register)
2
C bus interface interrupt each
TRCIC
SSUIC
IICIC
Interrupt Control
Register
12. Interrupts