R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet - Page 151

• Manufacturer Part Number: R5F21292SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21292SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
13.1
Table 13.2
NOTES:
Count source
Count operation
Period
Count start condition
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Specifications of Watchdog Timer (with Count Source Protection Mode Disabled).
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
0FFFFh with a flash programmer.
Count Source Protection Mode Disabled
Sep 26, 2008
Item
Specifications of Watchdog Timer (with Count Source Protection Mode Disabled)
Page 132 of 441
CPU clock
Decrement
Division ratio of prescaler (n) × count value of watchdog timer (32768)
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
The WDTON bit
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
• When the WDTON bit is set to 0 (watchdog timer starts automatically
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to 0
• When the PM12 bit in the PM1 register is set to 1
reset)
after exiting)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
The watchdog timer and prescaler start counting automatically after a
reset
Watchdog timer interrupt
Watchdog timer reset (Refer to 5.7 Watchdog Timer Reset)
divides by 16, the period is approximately 32.8 ms
(2)
in the OFS register (0FFFFh) selects the operation
Specification
CPU clock
13. Watchdog Timer
(1)