MC9S08DZ32ACLF Freescale Semiconductor, MC9S08DZ32ACLF Datasheet - Page 145
![IC MCU 32K FLASH 2K RAM 48-LQFP](/photos/12/36/123656/mc9s08dz32aclf_sml.jpg)
MC9S08DZ32ACLF
Manufacturer Part Number
MC9S08DZ32ACLF
Description
IC MCU 32K FLASH 2K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ32ACLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 16 channel
For Use With
EVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ32ACLF
Manufacturer:
FREESCALE
Quantity:
870
Company:
Part Number:
MC9S08DZ32ACLF
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC9S08DZ32ACLF
Manufacturer:
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Quantity:
20 000
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Freescale Semiconductor
Field
VDIV
CME
3:0
5
Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The
CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not
be changed.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.
VCO Divider — Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Reserved (default to M=40).
11xx Encoding 12-15 — Reserved (default to M=40).
Table 8-5. MCG PLL Register Field Descriptions (continued)
MC9S08DZ60 Series Data Sheet, Rev. 4
Description
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
145
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