MC908AP32ACFAE Freescale Semiconductor, MC908AP32ACFAE Datasheet - Page 222
![IC MCU 32K FLASH 8MHZ 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC908AP32ACFAE
Manufacturer Part Number
MC908AP32ACFAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP16ACFBER.pdf
(316 pages)
Specifications of MC908AP32ACFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP32ACFAE
Manufacturer:
FSC
Quantity:
15 000
Company:
Part Number:
MC908AP32ACFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Serial Peripheral Interface Module (SPI)
13.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to V
13.13 I/O Registers
Three registers control and monitor SPI operation:
13.13.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
222
•
•
•
•
•
•
•
•
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 13-4
identical CPOL values. Reset clears the CPOL bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address:
and
Reset:
Read:
Write:
Figure
SPRIE
$0010
Bit 7
0
13-6.) To transmit data between SPI modules, the SPI modules must have
SS
Figure 13-13. SPI Control Register (SPCR)
as shown in
= Unimplemented
MC68HC908AP A-Family Data Sheet, Rev. 3
R
6
0
SPMSTR
5
1
Table
13-1.
CPOL
4
0
CPHA
R
3
1
= Reserved
SPWOM
2
0
SPE
1
0
Freescale Semiconductor
SPTIE
Bit 0
0
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