M38039G6HSP#U0 Renesas Electronics America, M38039G6HSP#U0 Datasheet - Page 62

• Manufacturer Part Number: M38039G6HSP#U0
• Description: IC 740/3803 MCU QZROM 64DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039G6HSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H QzROM version)
REJ03B0166-0113 Rev.1.13
Page 60 of 100
PULSE WIDTH MODULATION (PWM)
The 3803 group (Spec.H QzROM version) has PWM functions
with an 8-bit resolution, based on a signal that is the clock input
X
that clock input divided by 2 in low-speed mode.
• Data Setting
The PWM output pin also functions as port P5
period by the PWM prescaler, and set the “H” term of output
pulse by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255):
PWM period = 255 × (n+1) / f(X
Output pulse “H” term = PWM period × m / 255
Fig 50. Block diagram of PWM function
IN
speed mode)
(X
or that clock input divided by 2 or the clock input X
CIN
= 31.875 × (n+1) µs
(when f(X
= 0.125 × (n+1) × m µs
(when f(X
at low-
X
IN
IN
IN
) = 8 MHz, count source selection bit = “0”)
) = 8 MHz, count source selection bit = “0”)
Data bus
1/2
“0”
Count source
selection bit
“1”
IN
)
Aug 21, 2009
prescaler pre-latch
PWM prescaler
prescaler latch
6
PWM
PWM
. Set the PWM
Transfer control circuit
CIN
or
register pre-latch
PWM register
• PWM Operation
When bit 0 (PWM function enable bit) of the PWM control
register is set to “1”, operation starts by initializing the PWM
output circuit, and pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Fig 49. Timing of PWM period
register latch
PWM output
PWM
PWM
m : Contents of PWM register
n : Contents of PWM prescaler
T : PWM period
(when f(X
31.875 × m × (n+1)
IN
) = 8 MHz, count source selection bit = “0”)
T = [31.875 × (n+1)] µ s
Port P5
255
PWM function enable bit
6
latch
µ s
Port P5
6