R5F21256SNFP#ES Renesas Electronics America, R5F21256SNFP#ES Datasheet - Page 134
R5F21256SNFP#ES
Manufacturer Part Number
R5F21256SNFP#ES
Description
MCU 2/5V 32K 52-LQFP ES SAMPLE
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21256SNFP#ES
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
12.2
Figure 12.12
12.2.1
External Input Enable Register
b7 b6 b5 b4
NOTES:
1.
2.
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register.
Inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff of timer RD and the external trigger input of timer
RB.
Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register.
INT Interrupt
When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4
Changing Interrupt Sources.
Feb 29, 2008
INTi Interrupt (i = 0 to 3)
b3 b2 b1 b0
INTEN Register
Bit Symbol
Symbol
INT0EN
INT1EN
INT2EN
INT3EN
INT0PL
INT1PL
INT2PL
INT3PL
INTEN
Page 115 of 485
_____
INT0
_____
INT0
_____
INT1
_____
INT1
_____
INT2
_____
INT2
_____
INT3
_____
INT3
input enable bit
input polarity select bit
input enable bit
input polarity select bit
input enable bit
input polarity select bit
input enable bit
input polarity select bit
Address
Bit Name
00F9h
(1,2)
(1,2)
(1,2)
(1,2)
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
0 : Disable
1 : Enable
0 : One edge
1 : Both edges
After Reset
Function
00h
12. Interrupts
RW
RW
RW
RW
RW
RW
RW
RW
RW
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