R5F21256SNFP#ES Renesas Electronics America, R5F21256SNFP#ES Datasheet - Page 380
R5F21256SNFP#ES
Manufacturer Part Number
R5F21256SNFP#ES
Description
MCU 2/5V 32K 52-LQFP ES SAMPLE
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21256SNFP#ES
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 16.44
16.3.5
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.44 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
f1 (sampling clock)
Feb 29, 2008
Noise Canceller
SCL or SDA
input signal
Block Diagram of Noise Canceller
Page 361 of 485
f1 (sampling clock)
Period of f1
D
Latch
C
Q
D
Latch
C
Q
16. Clock Synchronous Serial Interface
detection
Match
circuit
Internal SCL
or SDA signal
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