M38039GCHKP#U0 Renesas Electronics America, M38039GCHKP#U0 Datasheet - Page 17

• Manufacturer Part Number: M38039GCHKP#U0
• Description: IC 740/3803 MCU QZROM 64LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039GCHKP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H QzROM version)
REJ03B0166-0113 Rev.1.13
Page 15 of 100
MISRG
(1) Bit 0 of address 0010
(2) Bits 1, 2, 3 of address 0010
Fig 10. Structure of MISRG
set after STP instruction released bit
When the MCU stops the clock oscillation by the STP
instruction and the STP instruction has been released by an
external interrupt source, usually, the fixed values of Timer 1
and Prescaler 12 (Timer 1 = 01
automatically reloaded in order for the oscillation to
stabilize. The user can inhibit the automatic setting by setting
“1” to bit 0 of MISRG (address 0010
However, by setting this bit to “1”, the previous values, set
just before the STP instruction was executed, will remain in
Timer 1 and Prescaler 12. Therefore, you will need to set an
appropriate value to each register, in accordance with the
oscillation stabilizing time, before executing the STP
instruction.
Figure 10 shows the structure of MISRG.
Automatic Switch Function
In order to switch the clock mode of an MCU which has a
sub-clock, the following procedure is necessary:
set CPU mode register (003B
oscillation --> wait for oscillation stabilization --> switch to
middle-speed mode (or high-speed mode).
However, the 3803 group (Spec.H QzROM version) has the
built-in function which automatically switches from low to
middle-speed mode by program.
b7
Note : When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B
16
: Oscillation stabilizing time
16
16
16
, Prescaler 12 = FF
Aug 21, 2009
: Middle-speed Mode
) --> start main clock
16
).
b0
16
16
) are
) change.
MISRG
MISRG: address 0010
• Middle-speed mode automatic switch by program
Oscillation stabilizing time set after STP instruction
released bit
Middle-speed mode automatic switch set bit
Middle-speed mode automatic switch wait time set bit
Middle-speed mode automatic switch start bit
(Depending on program)
Not used (return “0” when read)
(Do not write “1” to this bit)
0 : Automatically set “01
1 : Automatically set disabled
0 : Not set automatically
1 : Automatic switching enabled (Note)
0 : 4.5 to 5.5 machine cycles
1 : 6.5 to 7.5 machine cycles
0 : Invalid
1 : Automatic switch start (Note)
The middle-speed mode can also be automatically switched
by program while operating in low-speed mode. By setting
the middle-speed automatic switch start bit (bit 3) of MISRG
(address 0010
speed mode automatic switch set bit is “1” while operating in
low-speed mode, the MCU will automatically switch to
middle-speed mode. In this case, the oscillation stabilizing
time of the main clock can be selected by the middle-speed
automatic switch wait time set bit (bit 2) of MISRG (address
0010
Prescaler 12
16
).
16
) to “1” in the condition that the middle-
16
)
16
” to Timer 1, “FF
16
” to