MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 348

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (IIC)
Reading the IICD will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST (Start bit) or
assertion of RSTA bit (repeated Start ) is used for the address transfer and should comprise of the calling
address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0).
15.3.7
15-10
AD[10:8]
Reset
GCAEN
ADEXT
Field
2:0
7
6
W
R
GCAEN
IIC Control Register 2 (IICC2)
General Call Address Enable — The GCAEN bit enables or disables general call address.
0 General call address is disabled
1 General call address is enabled.
Address Extension — The ADEXT bit controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
Slave Address — The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address
scheme. This field is only valid when the ADEXT bit is set.
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
= Unimplemented or Reserved
ADEXT
0
6
Figure 15-7. IIC Control Register (IICC2)
Table 15-8. IICC2 Field Descriptions
0
0
5
0
0
4
NOTE
Description
3
0
0
AD10
0
2
Freescale Semiconductor
AD9
0
1
AD8
0
0