M38039GCHSP#U0 Renesas Electronics America, M38039GCHSP#U0 Datasheet - Page 29

• Manufacturer Part Number: M38039GCHSP#U0
• Description: IC 740/3803 MCU QZROM 64DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039GCHSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H QzROM version)
REJ03B0166-0113 Rev.1.13
Page 27 of 100
INTERRUPTS
The 3803 group (Spec.H QzROM version) interrupts are vector
interrupts with a fixed priority scheme, and generated by 16
sources among 21 sources: 8 external, 12 internal, and 1
software.
The interrupt sources, vector addresses
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 20 shows an interrupt control diagram.
Table 8
NOTES:
Reset
INT
Timer Z
INT
Serial I/O1 reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 1
Timer 2
CNTR
CNTR
Serial I/O3 reception
Serial I/O2
Timer Z
INT
INT
INT
CNTR
A/D conversion
Serial I/O3
transmission
BRK instruction
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Interrupt Source
0
1
2
3
4
(2)
0
1
2
Interrupt vector addresses and priority
Priority
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
FFED
FFDD
FFFD
FFFB
FFEF
FFEB
FFDF
FFF9
FFF7
FFF5
FFF3
FFF1
FFE9
FFE7
FFE5
FFE3
FFE1
High
Addresses
Aug 21, 2009
(1)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Vector
16
16
, and interrupt priority
FFEC
FFDE
FFDC
FFFC
FFFA
FFEE
FFEA
FFE8
FFE6
FFE4
FFE2
FFE0
FFF8
FFF6
FFF4
FFF2
FFF0
Low
(1)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset
At detection of either rising or falling
edge of INT
At timer Z underflow
At detection of either rising or falling
edge of INT
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or falling
edge of CNTR
At detection of either rising or falling
edge of CNTR
At completion of serial I/O3 data
reception
At completion of serial I/O2 data
transmission or reception
At timer Z underflow
At detection of either rising or falling
edge of INT
At detection of either rising or falling
edge of INT
At detection of either rising or falling
edge of INT
At detection of either rising or falling
edge of CNTR
At completion of A/D conversion
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
At BRK instruction execution
Interrupt Request Generating
0
1
2
3
4
input
input
input
input
input
Conditions
0
1
2
An interrupt requests is accepted when all of the following
conditions are satisfied:
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
input
input
input
• Interrupt disable flag.................................“0”
• Interrupt request bit...................................“1”
• Interrupt enable bit....................................“1”
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
Non-maskable software interrupt
Remarks