M38039GCHSP#U0 Renesas Electronics America, M38039GCHSP#U0 Datasheet - Page 42

• Manufacturer Part Number: M38039GCHSP#U0
• Description: IC 740/3803 MCU QZROM 64DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039GCHSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H QzROM version)
REJ03B0166-0113 Rev.1.13
Page 40 of 100
(6) Programmable waveform generating mode
• Mode selection
This mode can be selected by setting “100” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(X
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(X
count source.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A
each time the timer underflows.
Changing the value of the output level latch and the timer latch
after an underflow makes it possible to output an optional
waveform from the CNTR
• Precautions
The double-function port of CNTR
automatically set to the programmable waveform generating port
in this mode.
Figure 34 shows the timing chart of the programmable waveform
generating mode.
16
CIN
).
2
); or f(X
pin.
CIN
Aug 21, 2009
16
) can be selected as the
IN
2
) from the CNTR
pin and port P4
); or f(X
CIN
) can be
2
7
pin
is
(7) Programmable one-shot generating mode
• Mode selection
This mode can be selected by setting “101” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(X
selected as the count source.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the INT
active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT
interrupt request bit (bit 1) of the interrupt request register 1
(address 003C
• Explanation of operation
• Precautions
Set the double-function port of INT
this mode.
The double-function port of CNTR
automatically set to the programmable one-shot generating port
in this mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR
during one-shot generating enabled or generating one-shot pulse,
then the output level from CNTR
Figure 35 shows the timing chart of the programmable one-shot
generating mode.
1. “H” one-shot pulse; Bit 5 of timer Z mode register = “0”
2. “L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR
mode selection. When trigger generation (input signal to
INT
When an underflow occurs, “L” is output. The “H” one-shot
pulse width is set by the setting value to the timer Z register
low-order and high-order. When trigger generating is
detected during timer count stop, although “H” is output
from the CNTR
underflow does not occur.
The output level of the CNTR
mode selection. When trigger generation (input signal to
INT
When an underflow occurs, “H” is output. The “L” one-shot
pulse width is set by the setting value to the timer Z low-
order and high-order. When trigger generating is detected
during timer count stop, although “L” is output from the
CNTR
flow does not occur.
1
1
pin) is detected, “H” is output from the CNTR
pin) is detected, “L” is output from the CNTR
2
pin, “L” output state continues because an under-
16
) is set to “1”.
2
16
16
pin, “H” output state continues because an
). When it is “0”, the falling edge active is
).
2
active edge switch bit is changed
2
pin changes.
1
1
2
2
pin is detected, the INT
pin and port P4
pin is initialized to “H” at
pin is initialized to “L” at
IN
2
pin and port P4
); or f(X
CIN
2
to input in
) can be
2
2
pin.
pin.
7
is
1
1