DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 122
![MCU 3V 16K 32-QFN](/photos/12/38/123805/32-qfn_pkg_sml.jpg)
DF38602RFT10
Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet
1.DF38602RFT10.pdf
(554 pages)
Specifications of DF38602RFT10
Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10
HD64F38602RFT10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
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Section 5 Power-Down Modes
5.2.2
In standby mode, the system clock oscillator stops, and the CPU and on-chip peripheral modules
stop functioning except for the WDT, asynchronous event counter, and comparators. However, as
long as the rated voltage is supplied, the contents of CPU registers and some on-chip peripheral
module registers are retained. On-chip RAM contents will be retained as long as the voltage set by
the RAM data retention voltage is provided. The I/O ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is
cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made
to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2.
Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by
the interrupt enable bit.
When a reset source is generated in standby mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the t
driven high.
5.2.3
In watch mode, the system clock oscillator and CPU operation stop, and on-chip peripheral
modules stop functioning except for the WDT, RTC, timer B1, asynchronous event counter, and
comparators. However, as long as the rated voltage is supplied, the contents of CPU registers,
some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain
their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When a reset source is generated in watch mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the t
driven high.
Rev. 3.00 May 15, 2007 Page 88 of 516
REJ09B0152-0300
REL
REL
Standby Mode
Watch Mode
period has elapsed. The CPU starts reset exception handling when the RES pin is
period has elapsed. The CPU starts reset exception handling when the RES pin is
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