DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 300

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.3
Figure 14.10 shows an example of SCI3 operation for transmission in clock synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at
3. 8-bit data is sent from the TXD3 pin synchronized with the output clock when output clock
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
7. The SCK3 pin is fixed high.
Figure 14.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Rev. 3.00 May 15, 2007 Page 266 of 516
REJ09B0152-0300
Figure 14.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode
TDRE
TEND
LSI
operation
User
processing
has been written to TDR, and transfers the data from TDR to TSR.
this time, a TXI3 interrupt request is generated.
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD3
pin.
Serial
clock
Serial
data
of the next frame is started.
the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI3 interrupt
request is generated.
TXI3
interrupt
request
generated
Serial Data Transmission
Bit 0
Bit 1
TDRE flag
cleared
to 0
Data written
to TDR
1 frame
TXI3 interrupt request
generated
Bit 7
Bit 0
Bit 1
1 frame
TEI3 interrupt request
generated
Bit 6
Bit 7