R5F212BASNFA#U0 Renesas Electronics America, R5F212BASNFA#U0 Datasheet - Page 21
Manufacturer Part Number
IC R8C/2B MCU FLASH 96+2K 64LQFP
Renesas Electronics America
Specifications of R5F212BASNFA#U0
I²C, LIN, SIO, SSU, UART/USART
POR, PWM, Voltage Detect, WDT
Number Of I /o
Program Memory Size
96KB (96K x 8)
Program Memory Type
7K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
A/D 12x10b; D/A 2x8b
-20°C ~ 85°C
Package / Case
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
R8C/2A Group, R8C/2B Group
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
If necessary, set to 0. When read, the content is undefined.
Nov 26, 2007
Interrupt Enable Flag (I)
Stack Pointer Select Flag (U)
Processor Interrupt Priority Level (IPL)
Page 19 of 60
2. Central Processing Unit (CPU)