MC9S12C32CFAE16 Freescale Semiconductor, MC9S12C32CFAE16 Datasheet - Page 151

• Manufacturer Part Number: MC9S12C32CFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 16MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: HCS12
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

4.4.2
In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the
HCS12 supports the concept of stretched bus cycles (module timing reference clocks for timers and baud
rate generators are not affected by this stretching). Control bits in the MISC register in the MMC sub-block
of the core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). While
stretching, the CPU state machines are all held in their current state. At this point in the CPU bus cycle,
write data would already be driven onto the data bus so the length of time write data is valid is extended
in the case of a stretched bus cycle. Read data would not be captured by the system until the E clock falling
edge. In the case of a stretched bus cycle, read data is not required until the specified setup time before the
falling edge of the stretched E clock. The chip selects, and R/W signals remain valid during the period of
stretching (throughout the stretched E high time).
4.4.3
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
Freescale Semiconductor
(Table
MODC
0
0
0
0
1
1
1
1
Stretched Bus Cycles
Modes of Operation
4-16). The MODC, MODB, and MODA bits in the MODE register show the current operating
The address portion of the bus cycle is not stretched
MODB
LSTRB
0
0
1
1
0
0
1
1
0
1
0
1
Table 4-15. Access Type vs. Bus Control Pins
MODA
AB0
0
1
0
1
0
1
0
1
0
1
0
1
MC9S12C-Family / MC9S12GC-Family
Table 4-16. Mode Selection
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause bus conflicts
(must not be used)
Normal Expanded Wide, BDM allowed
R/W
1
1
0
0
Rev 01.24
NOTE
16-bit read of an even address
16-bit read of an odd address
(low/high data swapped)
16-bit write to an even address
16-bit write to an odd address
(low/high data swapped)
Chapter 4 Multiplexed External Bus Interface (MEBIV3)
Mode Description
Type of Access
.
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