MCF5328CVM240J Freescale Semiconductor, MCF5328CVM240J Datasheet - Page 25

• Manufacturer Part Number: MCF5328CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5328CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.7.2
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.
Freescale Semiconductor
Num
DD1
DD2
DD3
DD4
DD5
DD6
DD7
•
SD_SDR_DQS
SD_DQS[3:2]
SD_BA[1:0]
SD_RAS,
SD_CAS,
SD_CSn,
Memories
Frequency of Operation
Clock Period
Pulse Width High
Pulse Width Low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS) Relative
to DQS (DDR Write Mode)
SD_CLK
SD_WE
SD_CLK
Delayed
A[23:0],
D[31:0]
SDDM
from
DDR SDRAM AC Timing Characteristics
(Measured at Output Pin)
(Measured at Input Pin)
NOTE: Data driven from memories relative
1
SD4
3
2
to delayed memory clock.
Characteristic
ROW
CMD
MCF532x ColdFire
3
4, 5
SD1
Table 11. DDR Timing Specifications
SD5
Figure 10. SDR Read Timing
®
COL
3/4 MCLK
Reference
Microprocessor Data Sheet, Rev. 5
Board Delay
Board Delay
tDQS
t
t
t
Symbol
SDCHACV
SDCHACI
CMDVDQ
t
t
t
DDCKH
DQDMV
t
t
DDCKL
SD10
DDCK
DDSK
WD1
SD2
SD6
SD9
12.5
0.45
0.45
Min
2.0
1.5
60
—
—
WD2
SD7
0.5 × SD_CLK
Electrical Characteristics
SD8
WD3
16.67
+ 1.0
Max
0.55
0.55
1.25
80
—
—
SD3
WD4
SD_CLK
SD_CLK
SD_CLK
Unit
Mhz
ns
ns
ns
ns
25