M30280F6HP#D5 Renesas Electronics America, M30280F6HP#D5 Datasheet - Page 10

• Manufacturer Part Number: M30280F6HP#D5
• Description: IC M16C MCU FLASH 48K 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Quick Reference by Address ........................................................................... B-1
1. Overview ......................................................................................................... 1
2. Central Processing Unit (CPU) ......................................................................22
3. Memory ..........................................................................................................24
4. Special Function Register (SFR) ....................................................................25
1.1 Features ........................................................................................................................... 1
1.2 Block Diagram .................................................................................................................. 4
1.3 Product Information .......................................................................................................... 6
1.4 Pin Assignment ............................................................................................................... 10
1.5 Pin Description ............................................................................................................... 19
2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 22
2.2 Address Registers (A0 and A1) ...................................................................................... 22
2.3 Frame Base Register (FB) .............................................................................................. 23
2.4 Interrupt Table Register (INTB) ....................................................................................... 23
2.5 Program Counter (PC) .................................................................................................... 23
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .......................................... 23
2.7 Static Base Register (SB) ............................................................................................... 23
2.8 Flag Register (FLG) ........................................................................................................ 23
1.1.1 Applications ................................................................................................................ 1
1.1.2 Specifications ............................................................................................................. 2
2.8.1 Carry Flag (C Flag) .................................................................................................. 23
2.8.2 Debug Flag (D Flag) ................................................................................................. 23
2.8.3 Zero Flag (Z Flag) ................................................................................................... 23
2.8.4 Sign Flag (S Flag) .................................................................................................... 23
2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 23
2.8.6 Overflow Flag (O Flag) ............................................................................................. 23
2.8.7 Interrupt Enable Flag (I Flag) ................................................................................... 23
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 23
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 23
2.8.10 Reserved Area ....................................................................................................... 23
Table of Contents
A-1