M30263F6AFP#U5 Renesas Electronics America, M30263F6AFP#U5 Datasheet - Page 52
![MCU 3/5V 48K PB-FREE 42-SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U5
Manufacturer Part Number
M30263F6AFP#U5
Description
MCU 3/5V 48K PB-FREE 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M
R
R
e
E
1
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J
6
Figure 5.5.1.1 Power Supply Down Detection Interrupt Generation Block
Figure 5.5.1.2 Power Supply Down Detection Interrupt Generation Circuit Operation Example
0
C
2
9
2 /
0 .
B
NOTES :
Voltage Down Detection Circuit
VCC
VREF
VCC
VC13 bit in VCR1 register
Output of the digital filter
D42 bit in D4INT register
Voltage down detection
interrupt signal
Watchdog Timer Block
0
0
6
2
A
0
F
1. D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled).
2. Output of the digital filter is shown in Figure 5.5.1.1.
VC27
2
+
-
G
(Rejection Range:200 ns)
e
0 -
b
o r
1 .
2
0
u
, 5
Noise
Rejection
0
p
2
(
0
M
0
WAIT instruction(wait mode)
1
7
(2)
6
The Voltage down detection
signal becomes “H” when the
VC27 bit is set to “0” (disabled)
Watchdog timer
underflow signal
C
2 /
page 33
6
, A
Voltage down
detection signal
D4INT clock(the
clock with which it
operates also in
wait mode)
VC13
CM10
CM02
M
1
f o
6
C
3
sampling
2 /
2
Voltage down detection interrupt generation circuit
9
6
1/8
, B
This bit is set to “0”(not detected) by program.
M
D43
1/2
1
6
C
1/2
2 /
6
Noise Rejection
Circuit
) T
sampling
1/2
00b
01b
10b
11b
DF1, DF0
D41
Digital
Filter
No voltage down detection interrupt signals are
generated when the D42 bit is “1”.
The D42 bit is set to “0” (not detected)
by program. the VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.
Set to “0” by program (not detected)
D42
sampling
D40
Watchdog
timer interrupt
signal
Oscillation stop,
re-oscillation
detection
interrupt signal
Voltage down
detection
interrupt signal
sampling
Non-maskable
interrupt signal
5. Reset
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