M30263F6AFP#U5 Renesas Electronics America, M30263F6AFP#U5 Datasheet - Page 73
![MCU 3/5V 48K PB-FREE 42-SSOP](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U5
Manufacturer Part Number
M30263F6AFP#U5
Description
MCU 3/5V 48K PB-FREE 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
. v
J
1
0
Figure 7.6.1. State Transition to Stop Mode and Wait Mode
6
2
9
C
0 .
B
2 /
0
Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.6.1.1 shows the state transition in normal operation mode.
Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
0
2
6
0
F
A
2
e
0 -
b
G
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1
(5)
1 .
2
o r
0
, 5
0
u
2
p
All oscillators stopped
0
(
0
M
7
CM05, CM06, CM07: Bits in the CM0 register
CM10, CM11: Bits in the CM1 register
NOTES:
1
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. When the PM21 bit is set to 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 bit is set to 0 (on-chip oscillator
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to 0 (oscillation stop and oscillation restart detection
7. The CM06 bit is set to 1 (divide-by-8).
Stop mode
Stop mode
Stop mode
Stop mode
6
Stop mode
Stop mode
turned off). When the clock generated externally is input to the X
function disabled).
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
C
page 54
2 /
6
, A
M
Interrupt
f o
1
CM10=1
CM10=1
CM10=1
CM10=1
CM10=1
Interrupt
Interrupt
CM10=1
6
Interrupt
Interrupt
Interrupt
3
C
2
9
2 /
(6)
(6)
(6)
(6)
(6)
(4)
(6)
(4)
6
, B
CM21=0
M
1
6
C
2 /
On-chip oscillator mode
Normal operation mode
(selectable frequency)
6
Low power dissipation mode
On-chip oscillator low power
dissipation mode
) T
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
On-chip oscillator
mode (f
High-speed, medium-
speed mode
Reset
CIN
2
(7)
(ROC)
pin, transit to stop mode with this process.
PLL operation
mode
/16)
(1, 2)
CM21=1
WAIT
instruction
WAIT
instruction
Interrupt
WAIT
instruction
WAIT
instruction
WAIT
instruction
WAIT
instruction
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
7. Clock Generation Circuit
CPU operation stopped
Wait mode
Wait mode
Wait mode
Wait mode
Wait mode
Wait mode
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