C8051F017-GQ Silicon Laboratories Inc, C8051F017-GQ Datasheet - Page 93

• Manufacturer Part Number: C8051F017-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F017-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 8
• Ram Memory Size: 256Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1196

13. RESET SOURCES
The reset circuitry of the MCUs allows the controller to be easily placed in a predefined default condition. On entry
to this reset state, the CIP-51 halts program execution, forces the external port pins to a known state and initializes
the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the program counter (PC) is
reset, and program execution starts at location 0x0000.
All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR detailed
descriptions. The contents of internal data memory are not changed during a reset and any previously stored data is
preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the
stack are not altered.
The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the external I/O
pins to a high state. The weak pull-ups are enabled during and after the reset. If the source of reset is from the VDD
Monitor or writing a 1 to PORSF, the /RST pin is driven low until the end of the VDD reset timeout.
On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by default.
Refer to Section 14 for information on selecting and configuring the system clock source. The Watchdog Timer is
enabled using its longest timeout interval. (Section 13.8 details the use of the Watchdog Timer.)
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external
CNVSTR signal, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset
source is described below:
93
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
(Port
I/O)
CP0+
CP0-
Crossbar
System
Clock
Comparator 0
CNVSTR
+
-
Detector
CNVRSEF
Missing
Clock
(one-
shot)
EN
Figure 13.1. Reset Sources Diagram
C0RSEF
EN
WDT
PRE
Rev. 1.7
VDD
CIP-51
Core
Supply
Monitor
+
-
(Software Reset)
SWRSF
System Reset
Timeout
Supply
Reset
(wired-OR)
Reset
Funnel
/RST