C8051F010-GQ Silicon Laboratories Inc, C8051F010-GQ Datasheet - Page 105

• Manufacturer Part Number: C8051F010-GQ
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F010-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1191

In the Priority Decode Table, a dot () is used to show the external Port I/O pin (column) to which each signal (row)
can be assigned by the user application code via programming registers XBR2, XBR1, and XBR0.
105
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SDA
SCL
SCK
MISO
MOSI
NSS
TX
RX
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
/SYSCLK
CNVSTR
PIN I/O 0




             
              
               
                
                 
                  
                   
                    
                     
                      
                       




1





2





3
P0





4
Table 15.1. Crossbar Priority Decode
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


5




6



7



0


1
Rev. 1.7


2

3
P1

4
5
6
7
0
1
2
3
P2
4
5
6
7