MC908GP32CBE Freescale Semiconductor, MC908GP32CBE Datasheet - Page 78
![IC MCU 32K FLASH 8MHZ 42-SDIP](/photos/12/39/123977/mc908gp32cbe_sml.jpg)
MC908GP32CBE
Manufacturer Part Number
MC908GP32CBE
Description
IC MCU 32K FLASH 8MHZ 42-SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908GP32CBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
31
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GP32CBE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MC908GP32CBE
Manufacturer:
F
Quantity:
20 000
Clock Generator Module (CGM)
5.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
5.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz.
Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the
100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error
between the actual output and the desired output to within specified tolerances. Therefore, the acquisition
or lock time varies according to the original error in the output. Minor errors may not even be registered.
Typical PLL applications prefer to use this definition because the system requires the output frequency to
be within a certain tolerance of the desired frequency regardless of the size of the initial error.
5.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, f
.
RDV
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency f
and the
XCLK
R value programmed in the reference divider. (See
5.3.3 PLL
Circuits,
5.3.6 Programming the
PLL, and
5.5.6 PLL Reference Divider Select
Register.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by
adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size
of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make
small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL
may not be able to adjust the voltage in a reasonable time. (See
5.8.3 Choosing a
Filter.)
Also important is the operating voltage potential applied to V
. The power supply potential alters the
DDA
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
MC68HC908GP32 Data Sheet, Rev. 10
78
Freescale Semiconductor