MCF52233CAL60 Freescale Semiconductor, MCF52233CAL60 Datasheet - Page 44
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MCF52233CAL60
Manufacturer Part Number
MCF52233CAL60
Description
IC MCU 256K FLASH 60MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5223xr
Datasheet
1.MCF52236AF50.pdf
(55 pages)
Specifications of MCF52233CAL60
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
60MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Cpu Family
MCF5223x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
60MHz
Interface Type
I2C/QSPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
10
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Processor Series
MCF522x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
32 KB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
56
Number Of Timers
10
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52235EVB, M52233DEMO
Minimum Operating Temperature
- 40 C
Package
112LQFP
Family Name
MCF5223x
Maximum Speed
60 MHz
Operating Supply Voltage
3.3 V
For Use With
M52233DEMO - BOARD DEMO FOR MCF52233
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52233CAL60
Manufacturer:
FREESCAL
Quantity:
1 000
Company:
Part Number:
MCF52233CAL60
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
2.13
44
1
Num
J10
J11
J12
J13
J14
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J1
J2
J3
J4
J5
J6
J7
J8
J9
JTAG and Boundary Scan Timing
TCLK
(input)
TCLK frequency of operation
TCLK cycle period
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high Z
TRST assert time
TRST setup time (negation) to TCLK high
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Characteristics
Table 39. JTAG and Boundary Scan Timing
J4
V
IH
Figure 14. Test Clock Input Timing
V
IL
1
J3
J4
J2
Symbol
t
t
t
t
t
t
t
t
TAPBST
TAPBHT
TRSTST
TRSTAT
TDODZ
f
t
BSDST
BSDHT
t
t
TDODV
t
t
JCYC
JCYC
BSDV
BSDZ
JCRF
JCW
J3
4 t
Min
100
DC
26
26
10
10
0
4
0
0
4
0
0
CYC
Freescale Semiconductor
Max
1/4
33
33
26
—
—
—
—
—
—
—
—
3
8
f
Unit
sys/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns