MCF52233CAL60 Freescale Semiconductor, MCF52233CAL60 Datasheet - Page 9
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MCF52233CAL60
Manufacturer Part Number
MCF52233CAL60
Description
IC MCU 256K FLASH 60MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5223xr
Datasheet
1.MCF52236AF50.pdf
(55 pages)
Specifications of MCF52233CAL60
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
60MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Cpu Family
MCF5223x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
60MHz
Interface Type
I2C/QSPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
10
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Processor Series
MCF522x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
32 KB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
56
Number Of Timers
10
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52235EVB, M52233DEMO
Minimum Operating Temperature
- 40 C
Package
112LQFP
Family Name
MCF5223x
Maximum Speed
60 MHz
Operating Supply Voltage
3.3 V
For Use With
M52233DEMO - BOARD DEMO FOR MCF52233
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52233CAL60
Manufacturer:
FREESCAL
Quantity:
1 000
Company:
Part Number:
MCF52233CAL60
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
pipeline, optimized for 1616 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and
32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types.
The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
1.2.3
The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and
emulator development tools. Through a standard debug interface, access debug information and real-time tracing capability is
provided on 112-and 121-lead packages. This allows the processor and system to be debugged at full speed without the need
for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF52235 implements revision B+ of the ColdFire Debug Architecture.
The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining
processor activity at the CPU’s clock rate. The MCF52235 includes a new debug signal, ALLPST. This signal is the logical
AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] =
1111).
The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product features the dedicated
debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4
The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and
three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register
links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device
system logic.
The MCF52235 implementation can do the following:
1.2.5
1.2.5.1
The dual-ported SRAM module provides a general-purpose 16- or 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 16- or 32-Kbyte boundary within the 4-Gbyte address
space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM
Freescale Semiconductor
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Perform boundary-scan operations to test circuit board electrical continuity
Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register
Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
Integrated Debug Module
JTAG
On-Chip Memories
SRAM
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
MCF52235 Family Configurations
9