M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 257
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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M
R
R
1
e
E
Table 15.9 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
Figure 15.18 ADTRGCON Register in Simultaneous Sample Sweep Mode
. v
6
NOTES:
J
0
C
TRG
2
1. A count can be started for Timer B2, Timer B2 interrupt generation frequency
2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter
9
2 /
0 .
0
1
1
1
B
0
8
0
setting counter underflow or the INT5 pin falling edge as count start
conditions of Timer B0.
using the TB2SEL bit in the TB2SC register.
0
G
4
J
7
a
o r
0 -
TRG1
. n
u
1
0
2
-
-
A/D Trigger Control Register
NOTES:
p
3
b7
0
, 1
0
(
1. If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
M
b6
2
1
HPTRG0
0
b5
0
6
7
C
1
0
-
0
b4
2 /
page 235
, 8
b3
0
M
b2
Software trigger
AD
Timer B2 or Timer B2 interrupt generation frequency setting
counter underflow
Timer B0 underflow
1
0
b1
TRG
6
C
b0
1
2 /
f o
8
TRIGGER
Bit Symbol
3
) B
HPTRG0
HPTRG1
(b7-b4)
8
5
SSE
DTE
Symbol
ADTRGCON
(1)
(2)
(1)
AN0 Trigger Select Bit
A/D Operation Mode
Select Bit 2
A/D Operation Mode
Select Bit 3
AN1 Trigger Select Bit
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Bit Name
Address
03D2
16
After Reset
00
Set to "0" in simultaneous sample
sweep mode
0 : Any mode other than delayed trigger
Refer to Table 15.9
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
16
mode 0,1
Function
15. A/D Converter
RW
RW
RW
RW
RW
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