M30280FAHP#D5 Renesas Electronics America, M30280FAHP#D5 Datasheet - Page 340
M30280FAHP#D5
Manufacturer Part Number
M30280FAHP#D5
Description
IC M16C MCU FLASH 96K 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280FAHP#D5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
For Use With
M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
M30280FAHP#D5A
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M
R
R
18.8 Status Register
1
e
E
Table 18.6 Status Register
. v
6
J
SRD register
• D
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to "1", the program and block erase command are not accepted.
18.8.1 Sequence Status (SR7 and FMR00 Bits )
18.8.2 Erase Status (SR5 and FMR07 Bits)
18.8.3 Program Status (SR4 and FMR06 Bits)
0
C
Bits in the
2
9
SR7 (D
SR6 (D
SR5 (D
SR4 (D
SR3 (D
SR2 (D
SR1 (D
SR0 (D
The status register indicates the operating status of the flash memory and whether or not erase or pro-
gram operation is successfully completed. The FMR00, FMR06, and FMR07 bits in the FMR0 register
indicate the status of the status register.
Table 18.6 lists the status register.
In EW mode 0, the status register can be read in the following cases:
The sequence status indicates the flash memory operating status. It is set to “0” (busy) while the auto-
program and auto-erase operation is being executed and “1” (ready) as soon as these operations are
completed. This bit indicates “0” (busy) in erase-suspend mode.
Refer to 18.8.4 Full Status Check.
Refer to 18.8.4 Full Status Check.
2 /
0 .
B
7
8
0
0
(1) Any even address in the user ROM area is read after writing the read status register command
(2) Any even address in the user ROM area is read from when the program or block erase command is
to D
0
G
4
J
executed until when the read array command is executed.
7
a
o r
0 -
. n
0
7
6
5
4
3
2
1
0
u
: Indicates the data bus which is read out when executing the read status register command.
)
)
)
)
)
)
)
)
2
p
3
0
, 1
0
(
M
Bits in the
2
register
0
1
FMR00
FMR07
FMR06
FMR0
0
6
7
C
2 /
page 318
, 8
M
1
6
Reserved
Program status
Reserved
Reserved
Reserved
Reserved
Sequence status
Erase status
C
Status name
2 /
f o
8
3
) B
8
5
Completed normally
Completed normally
Busy
"0"
-
-
-
-
-
Contents
Terminated by error
Terminated by error
Ready
"1"
-
-
-
-
-
18. Flash Memory Version
Value
reset
after
1
0
0
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