DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 397
![MCU 3/5V 32K J-TEMP PB-FREE 64-Q](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.4.5
Initialization in Clocked Synchronous Communication Mode: Figure 16.4 shows the
initialization in clocked synchronous communication mode. Before transmitting and receiving
data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Operation in Clocked Synchronous Communication Mode
Figure 16.4 Initialization in Clocked Synchronous Communication Mode
Clear CPOS and CPHS bits to 0 and set
MLS and CKS2 to CKS0 bits in SSMR
Set the TE and RE bits in SSER to 1
reception/transmission and reception
and set RIE, TIE, TEIE, and RSSTP
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSCRL to 0
bits according to transmission/
Set SCKS bit in SSCRH to 1
Clear ORER bit in SSSR to 0
and set MSS and SOOS bits
Section 16 Synchronous Serial Communication Unit (SSU)
Start
End
Rev. 4.00 Mar. 15, 2006 Page 363 of 556
REJ09B0026-0400
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