HD64F3644WV Renesas Electronics America, HD64F3644WV Datasheet - Page 305
HD64F3644WV
Manufacturer Part Number
HD64F3644WV
Description
IC H8/3644 MCU FLASH 80TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644WV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3644WV
Manufacturer:
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Quantity:
10 000
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Bit 0 Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to
start transferring data.
During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared
to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0: STF
0
1
Serial Data Register U (SDRU)
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this register
is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is undefined.
Serial Data Register L (SDRL)
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
SDRU7
SDRL7
R/W
R/W
Read: Indicates that transfer is stopped
Write: Invalid
Read: Indicates transfer in progress
Write: Starts a transfer operation
Description
7
7
SDRU6
SDRL6
R/W
R/W
6
6
SDRU5
SDRL5
R/W
R/W
5
5
SDRU4
SDRL4
R/W
R/W
4
4
Section 10 Serial Communication Interface
Rev. 6.00 Sep 12, 2006 page 283 of 526
SDRU3
SDRL3
R/W
R/W
3
3
SDRU2
SDRL2
R/W
R/W
2
2
SDRU1
REJ09B0326-0600
SDRL1
R/W
R/W
1
1
(initial value)
SDRU0
SDRL0
R/W
R/W
0
0
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