DF36034GFPJV Renesas Electronics America, DF36034GFPJV Datasheet - Page 275
![MCU 3/5V 32K J TEMP PB-FREE 64LQ](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJV
Manufacturer Part Number
DF36034GFPJV
Description
MCU 3/5V 32K J TEMP PB-FREE 64LQ
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Contention between GR Write and Input Capture: If an input capture signal is generated in the
T
performed. Figure 12.58 shows the timing in this case.
Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
1. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
2. Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice
2
WGR
(internal write signal)
state of a GR write cycle, the input capture operation has priority and the write to GR is not
versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the
normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
Address bus
Input capture
signal
TCNT
GR
Figure 12.58 Contention between GR Write and Input Capture
N
GR write cycle
T
GR address
1
T
2
Rev. 4.00 Mar. 15, 2006 Page 241 of 556
M
GR write data
Section 12 Timer Z
REJ09B0026-0400
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