HD6413003TF16 Renesas Electronics America, HD6413003TF16 Datasheet - Page 223
HD6413003TF16
Manufacturer Part Number
HD6413003TF16
Description
IC H8 MCU ROMLESS QFP112
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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8.4.4 Repeat Mode
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable
timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat
mode can be selected for each channel independently.
One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number
of these transfers are executed. One address is specified in the memory address register (MAR),
the other in the I/O address register (IOAR). At the end of the designated number of transfers,
MAR and ETCR are restored to their original values and operation continues. The direction of
transfer is determined automatically from the activation source. The transfer is from the address
specified in IOAR to the address specified in MAR if activated by an SCI receive-data-full
interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 8-8 indicates the register functions in repeat mode.
Table 8-8 Register Functions in Repeat Mode
Register
Legend
MAR:
IOAR: I/O address register
ETCR: Execute transfer count register
23
23
All 1s
Memory address register
MAR
7
7
7
ETCRH
ETCRL
IOAR
0
0
0
0
Activated by
SCI Receive-
Data-Full
Interrupt
Destination
address
register
Source
address
register
Transfer counter
Initial transfer count
Function
203
Other
Activation Initial Setting
Source
address
register
Destination Source or
address
register
Destination or
source address decremented at
destination
address
Number of
transfers
Number of
transfers
Operation
each transfer until
ETCRH reaches
H'0000, then restored
to initial value
Held fixed
Decremented once
per transfer unti
H'0000 is reached,
then reloaded from
ETCRL
Incremented or
Held fixed
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