C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 141
C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE
register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as
it did prior to the interrupts occurring. See Figure 11.9 below.
Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE,
SFRNEXT, and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is
possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct
access to the SFR Page stack can be useful to enable real-time operating systems to control and manage
context switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN). See SFR Definition 11.2.
Figure 11.9. SFR Page Stack Upon Return From ADC2 Window Interrupt
SFRNEXT
SFRPAGE
popped to
stack on return from
popped off of the
SFR Page 0x02
(Port 5)
Automatically
0x0F
interrupt
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFRPAGE
SFRNEXT
SFRLAST
141
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